Design and Implementation of FPGA based 64-bit MAC Unit using VEDIC Multiplier and Reversible Logic Gates
نویسندگان
چکیده
منابع مشابه
32-bit Mac Unit Design Using Vedic Multiplier
This paper presents Multiply and Accumulate (MAC) unit design using Vedic Multiplier, which is based on Urdhva Tiryagbhyam Sutra. The paper emphasizes an efficient 32-bit MAC architecture along with 8-bit and 16-bit versions and results are presented in comparison with conventional architectures. The efficiency in terms of area and speed of proposed MAC unit architecture is observed through red...
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ژورنال
عنوان ژورنال: Indian Journal of Science and Technology
سال: 2017
ISSN: 0974-5645,0974-6846
DOI: 10.17485/ijst/2017/v10i3/109413